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| IPA045N10N3 G OptiMOSTM3 Power-Transistor Features * N-channel, normal level * Excellent gate charge x R DS(on) product (FOM) * Very low on-resistance R DS(on) * 175 C operating temperature * Pb-free lead plating; RoHS compliant * Qualified according to JEDEC1) for target application Product Summary V DS R DS(on),max ID 100 4.5 64 V m A * Ideal for high-frequency switching and synchronous rectification Type IPA045N10N3 G Package Marking PG-TO220-FP 045N10N Maximum ratings, at T j=25 C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID T C=25 C2) T C=100 C Pulsed drain current2) Avalanche energy, single pulse Gate source voltage Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 1) 2) Value 64 45 256 540 20 Unit A I D,pulse E AS V GS P tot T j, T stg T C=25 C I D=64 A, R GS=25 mJ V W C T C=25 C 39 -55 ... 175 55/175/56 J-STD20 and JESD22 See figure 3 Rev. 2.2 page 1 2009-05-12 IPA045N10N3 G Parameter Symbol Conditions min. Values typ. max. Unit Thermal characteristics Thermal resistance, junction - case R thJC 3.8 K/W Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=150 A V DS=100 V, V GS=0 V, T j=25 C V DS=100 V, V GS=0 V, T j=125 C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=20 V, V DS=0 V V GS=10 V, I D=64 A V GS=6 V, I D=32 A Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=64 A 100 2 2.7 0.1 3.5 1 A V 60 10 1 3.9 4.7 1.4 119 100 100 4.5 7.7 S nA m 3) 2 Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. Rev. 2.2 page 2 2009-05-12 IPA045N10N3 G Parameter Symbol Conditions min. Values typ. max. Unit Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics 4) Gate to source charge Gate to drain charge Switching charge Gate charge total Gate plateau voltage Output charge Reverse Diode Diode continous forward current Diode pulse current Diode forward voltage Reverse recovery time Reverse recovery charge 4) C iss C oss C rss t d(on) tr t d(off) tf V DD=50 V, V GS=10 V, I D=64 A, R G=1.6 V GS=0 V, V DS=50 V, f =1 MHz - 6320 1100 41 25 47 50 15 8410 1460 - pF ns Q gs Q gd Q sw Qg V plateau Q oss V DD=50 V, V GS=0 V V DD=50 V, I D=64 A, V GS=0 to 10 V - 28 16 25 88 4.4 117 117 155 nC V nC IS I S,pulse V SD t rr Q rr T C=25 C V GS=0 V, I F=64 A, T j=25 C V R=50 V, I F=64 A, di F/dt =100 A/s - 0.9 69 140 64 256 1 - A V ns nC See figure 16 for gate charge parameter definition Rev. 2.2 page 3 2009-05-12 IPA045N10N3 G 1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); V GS10 V 50 70 60 40 50 30 P tot [W] 40 I D [A] 20 30 20 10 10 0 0 50 100 150 200 0 0 50 100 150 200 T C [C] T C [C] 3 Safe operating area I D=f(V DS); T C=25 C; D =0 parameter: t p 103 limited by on-state resistance 4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T 101 1 s 100 s 10 s 0.5 102 100 0.2 Z thJC [K/W] 1 ms I D [A] 0.1 10 1 10 ms 0.05 DC 10-1 0.02 100 0.01 single pulse 10-1 10 -1 10-2 10 0 10 1 10 2 10 3 10-5 10-4 10-3 10-2 10-1 100 101 V DS [V] t p [s] Rev. 2.2 page 4 2009-05-12 IPA045N10N3 G 5 Typ. output characteristics I D=f(V DS); T j=25 C parameter: V GS 250 10 V 7.5 V 6 Typ. drain-source on resistance R DS(on)=f(I D); T j=25 C parameter: V GS 10 6V 5.5 V 200 8 4.5 V 5V R DS(on) [m] 150 6 5V I D [A] 6V 7.5 V 100 4 10 V 4.5 V 50 2 0 0 1 2 3 4 5 0 0 20 40 60 80 100 V DS [V] I D [A] 7 Typ. transfer characteristics I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j 200 8 Typ. forward transconductance g fs=f(I D); T j=25 C 160 150 120 100 g fs [S] 25 C 175 C I D [A] 80 50 40 0 0 2 4 6 8 0 0 20 40 60 80 100 V GS [V] I D [A] Rev. 2.2 page 5 2009-05-12 IPA045N10N3 G 9 Drain-source on-state resistance R DS(on)=f(T j); I D=64 A; V GS=10 V 10 Typ. gate threshold voltage V GS(th)=f(T j); V GS=V DS parameter: I D 10 4 3.5 8 3 1500 A R DS(on) [m] 6 98 % typ 2.5 V GS(th) [V] 150 A 2 4 1.5 1 2 0.5 0 -60 -20 20 60 100 140 180 0 -60 -20 20 60 100 140 180 T j [C] T j [C] 11 Typ. capacitances C =f(V DS); V GS=0 V; f =1 MHz 12 Forward characteristics of reverse diode I F=f(V SD) parameter: T j 104 Ciss 103 Coss 103 102 25 C C [pF] I F [A] 175 C 175 C, 98% 25 C, 98% 102 Crss 101 101 0 20 40 60 80 100 0 0.5 1 1.5 2 V DS [V] V SD [V] Rev. 2.2 page 6 2009-05-12 IPA045N10N3 G 13 Avalanche characteristics I AS=f(t AV); R GS=25 parameter: T j(start) 100 14 Typ. gate charge V GS=f(Q gate); I D=64 A pulsed parameter: V DD 10 25 C 100 C 8 80 V 150 C 6 50 V 20 V 10 V GS [V] 4 2 0 1 10 100 1000 0 20 I AS [A] 1 40 60 80 100 t AV [s] Q gate [nC] 15 Drain-source breakdown voltage V BR(DSS)=f(T j); I D=1 mA 16 Gate charge waveforms 110 V GS Qg 105 V BR(DSS) [V] 100 V g s(th) 95 Q g(th) Q gs -60 -20 20 60 100 140 180 Q sw Q gd Q g ate 90 T j [C] Rev. 2.2 page 7 2009-05-12 IPA045N10N3 G PG-TO220-FP Rev. 2.2 page 8 2009-05-12 IPA045N10N3 G Published by Infineon Technologies AG 81726 Munich, Germany (c) 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 2.2 page 9 2009-05-12 |
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